As the dimensions of semiconductor device features continue to shrink into the deep submicron range, it becomes increasingly more difficult to form the features with high dimensional accuracy. The minimum size of a feature depends upon the chemical and optical limits of a particular lithography system, notably the depth of focus of a particular tool. Therefore, it is of utmost importance to provide an extremely flat wafer or substrate surface during fabrication of integrated circuits as well as other electronic devices.
Conventional practices include planarizing a substrate surface to remove high topography, surface defects, scratches or imbedded particles, as by CMP, which typically involves introducing a chemical slurry during polishing to facilitate higher removal rates and selectivity between films on the substrate surface. Typically, CMP involves holding a substrate against a polishing pad under controlled pressure, temperature and rotational speed of the pad in the presence of the slurry or other fluid medium. Typical pads are constructed with a proper balance between stiffness or rigidity for wafer smoothness and compressibility or flexibility for uniformity, as by forming a composite polishing pad with an upper rigid layer and an underlying flexible layer.
In accordance with conventional practices, a polishing pad 60 is provided, as illustrated in FIG. 6A, having a polishing surface comprising at least one concavity or aperture 61 adjacent a convexity or projection 62. The aperture or recessed portion of the surface pattern provides slurry on the wafer surface during CMP.
In accordance with conventional practices, the surface pattern containing aperture 61 and projection 62 is typically formed by mechanical, or chemical techniques. Subsequently, an adhesive layer 63 is adhered to the back surface of the polishing layer by application of pressure, such as rolling, illustrated in FIG. 6B. During rolling pressure is applied from both upper surface and lower surface as illustrated by arrows 64 and 65, respectively.
Such conventional techniques are problematic in that during application of the adhesive layer 63, which is typically a pressure sensitive adhesive, uniform pressure is not applied across the entire interface between the adhesive layer and the back surface of the polishing layer. This is because less pressure is applied to the recessed portion of the surface pattern B than the projection portion A during pressing. Therefore, adhesion between the adhesive layer and the back surface of the polishing layer underlying or corresponding to the recessed portion B is relatively weaker than adhesion between the adhesive layer and the back surface underlying projection portion A. During CMP, a sheer force is applied tending to delaminate the adhesive layer due to the weaker adhesion underlying portion B, thereby limiting the lifetime of the polishing pad. Moreover, delamination during CMP may damage the semiconductor wafer undergoing planarization.
Accordingly, a need exists for polishing pads having a surface pattern and an opposing mounting surface with an adhesive layer uniformly adhered thereto, and for methodology enabling the fabrication of such polishing pads. There exists a particular need for polishing pads having a surface pattern comprising apertures and projections and an opposing mounting surface with an adhesive layer adhered thereto with substantially uniform adhesive strength in regions corresponding to both the apertures and the projections, and for enabling methodology.